1. Field of the Invention
The present invention relates to a delay analysis result display device and particularly, to a delay analysis result display device for a logic circuit.
2. Description of the Prior Art
FIG. 11 is a general circuit diagram of a logic circuit. This circuit includes elements 21 to 28, and wires 31 to 35 each of which is connected between the elements. Elements 21 to 28 are electrically connected to wires 31 to 35 through pins P1 to P12. Each of elements 21, 24, 27, 28 consists of a flip-flop. It is assumed that information on an inter-pin delay time of each of elements in the circuit, a inter-pin delay time of each of wire in the circuit, etc. are beforehand stored in a delay analysis result display device.
It is now assumed that an operator inputs to the delay result display device a command to display a delay analysis result of the path between flip-flops 21 and 24.
FIG. 12 shows an example of a circuit diagram which is displayed on a screen of the delay analysis result display device. In response to the command, the delay analysis result display device displays such a circuit as shown in FIG. 12, and also displays a delay analysis result of this path (not shown).
In FIG. 12, only elements 21 to 24 and wires 31 to 33 connected therebetween are illustrated. Further, at the same time, the delay analysis result only for the circuit shown in FIG. 12 is displayed. An example of this type delay analysis system is disclosed in JPA-2-245879. This publication discloses as a prior art an analysis system comprising a CAD master file, an FF check program, an FF check result file, an analysis program, and a list.
According to the analysis system, circuit elements and wiring conditions stored in the CAD master file are used for path ready check between FFs (flip-flops) by an FF check program, the path ready check result thus obtained is outputted to the FF check result file, the data thus outputted are analyzed by batch process using an analysis program and the analysis result is output as a list. Among the members of the system, the FF check result file corresponds to the delay analysis result, and the list corresponds to the display device.
However, the conventional delay analysis result display device displays only a path which is obtained from the delay analysis result. That is, only elements 21 to 24 and wires 31 to 33 which are connected between the respective elements are displayed as shows in FIG. 12. Therefore, even when the circuit correction is intended to be performed on the basis of the delay analysis result, it needs a large labor to perform the circuit correction because the situation of adjoining circuits is unknown.
That is, in order to examine the situation of the adjoining circuits, it is needed to examine the corresponding path or wire by making reference to a circuit diagram on a paper or on a screen of a circuit diagram display device or the like, whereby large time is needed for the circuit correction.
The system disclosed in JPA-2-245879 never teaches means for solving the above problem.